library verilog;
use verilog.vl_types.all;
entity vga_sync is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        v_video_en      : out    vl_logic;
        h_video_en      : out    vl_logic;
        hsync           : out    vl_logic;
        vsync           : out    vl_logic;
        pixel_x         : out    vl_logic_vector(9 downto 0);
        pixel_y         : out    vl_logic_vector(9 downto 0)
    );
end vga_sync;
